1. Field of the Invention
The present invention relates to a method for making a multilayer wiring structure of a semiconductor integrated circuit.
2. Description of the Related Arts
Recently, the levels of integration in semiconductor integrated circuits are increasingly being raised. In accordance with this, devices formed on semiconductor substrates, such as active devices, are practically manufactured in increasingly finer sizes.
Meanwhile, although the performance of these devices is being improved along with improvements in fineness, wiring patterns interconnecting such devices cannot be narrowed in response to such improvements due to limitation such as those relating to electric current density. In one method to overcome this problem, devices are interconnected by employing a multilayer wiring structure. In a multilayer wiring structure, especially for an integrated circuit for a special use, such as a gate array type circuit, the number of the wiring layers reaches as many as 5, 6, or more. Accordingly, the number of connections between each device and each wiring pattern, or between wiring layers lying one upon another, is enormous.
In addition to narrowing the widths of the wiring patterns, the heights of the wiring patterns should also be lowered to reduce the capacitance between wiring patterns in the same wiring layer since LSI's are required to have low power demands and high performances. To meet this, wiring materials which have low electrical resistances and high electro-migration resistances, i.e. high allowable current densities, have been investigated. A typical example of such a material is copper. Since copper is poor in processability, a buried wiring structure obtained by employing a chemical mechanical polishing technique (CMP) has been proposed to improve current density by using copper.
FIG. 1 contains drawings illustrating a method for forming a multilayer wiring structure and achieving connections between wiring layers (via hole connections) according to the related art, which can achieve manufacture of semiconductor integrated circuits of the so called 0.25 .mu.m generation.
Initially, as shown in FIG. 1A, an insulation film 2 is formed on a substrate 1 on which active devices (not illustrated) have been formed, and a plurality of first wiring patterns 3 are then formed on the insulation film 2.
Next, as shown in FIG. 1B, an interlayer insulation film 4 is formed on the above-mentioned insulation film 2 so as to cover the above-mentioned first wiring patterns 3 by a technique of, for example, Ozone-TEOS-CVD or Plasma-enhanced TEOS-CVD (here, TEOS is the abbreviation of "tetraethoxysilane", and CVD is the abbreviation of "chemical vapor deposition"). This interlayer insulating film 4 insulates the first wiring patterns 3 and second wiring patterns to be formed afterwards. Ordinarily, a TEOS-CVD technique, in which a highly fluid material is used, is preferably employed to form the above-mentioned interlayer insulating film 4 since it is suitable to fill up the spaces between the first wiring patterns. Alternatively, an ECR-CVD technique or SOG technique are also employed (here, ECR is the abbreviation of "electron cyclotron resonance", and SOG is the abbreviation of "spin on glass").
Subsequently, a resist pattern (not illustrated) which has an openings only in a portion for connection between a first wiring pattern 3 and a second wiring pattern to be formed afterwards is formed by an ordinary photolithography technique. While using this resist pattern as an etching mask, a connecting hole 5 having a diameter of approximately 0.35 .mu.m is then formed in the interlayer insulating film 4 by reactive ion etching, and the resist pattern is removed.
After this, as shown in FIG. 1C, an adhering layer 6 is provided by sputtering, and further, as shown in FIG. 1D, an aluminum-based metal layer 7 is provided by sputtering to pack connecting metal and to form the second wiring pattern.
Here, in an integrated circuit which is highly finely manufactured and which has a high integration level, the aspect ratio of the connecting hole 5 is generally as high as approximately 2, and therefore, it is required to heat the aluminum-based metal up to 500.degree. C. or more and to pour such fluidized metal into the connecting hole 5 in order to sufficiently fill the connecting hole 5 with metal and secure conduction.
Next, the above-obtained aluminum-based metal layer 7 is subjected to patterning by an ordinary photolithography technique and an etching technique to obtain a desired wiring pattern containing the connecting portion.
Several methods can be employed for pouring the above-mentioned aluminum-based metal into the connecting hole. For example, a substrate 1 may be heated up to approximately 500.degree. C. on sputtering, and the pouring of metal into a connecting hole 5 is performed at the same time as an aluminum-based metal layer 7 is being formed. Alternatively, after a connecting hole 5 is formed, an aluminum-based metal layer 7 may be provided by sputtering in a highly vacuum atmosphere so as not to fill up the connecting hole 5, and the aluminum-based metal layer 7 is then pressed in a high pressure vessel at approximately 500.degree. C. and 20 MPa to force the metal into the connecting hole 5.
Further, tungsten (W) can be used in addition to an aluminum-based metal as a metal for filling a connecting hole and securing conduction. When tungsten is used in, for example, a LSI of the 0.25 .mu.m generation, even a connecting hole having a high aspect ratio such as of approximately 0.35 .mu.m in diameter and approximately 0.6 .mu.m in depth can be filled by a CVD technique in which surface reaction is the principal mechanism. In this case, tungsten is initially deposited over the entire surface of a substrate in which a connecting hole is formed, and tungsten in the plain portion only is removed by reactive ion etching to form a tungsten plug in the connecting hole. Next, by an ordinary deposition technique such as sputtering, aluminum-based metal is deposited and further subjected to patterning to obtain a second wiring pattern.
Any methods described above require providing a barrier metal or an adhering layer by sputtering or CVD before the connecting hole is filled with metal. In a case where the connecting hole is filled with an aluminum-based metal, the fluidity of the metal is reduced due to oxidation of aluminum when the metal comes into contact with an interlayer insulation film which contains an oxide compound. To avoid this, it is necessary to provide a barrier metal which comprises a thin film of titanium nitride (TiN). Meanwhile, adhesion of tungsten is low at the surface of an interlayer insulation film where an oxide thin film or the like is exposed, or at the side wall of the connecting hole. Accordingly, when tungsten is used, it is necessary to provide an adhering layer which comprises a thin film of titanium nitride in order to prevent peeling.
Moreover, adding copper to aluminum has been proposed as a method for improving the electro-migration resistance of an aluminum-based wiring pattern, and methods for increasing the content of copper have been offered. For example, a technique using aluminum-based metal which principally comprises aluminum and contains approximately 0.5% of copper having a mass greater than the aluminum is already known. Since scattering of aluminum by electrons occurs most intensively at aluminum grain boundaries, properly dispersing copper at the boundaries can reduce such scattering and brings about an inhibitory effect against breakage due to electro-migration.
Hereinafter, a typical example of an aluminum-based wiring structure which can achieve LSI's of the 0.25 .mu.m generation.
In LSI's of the 0.25 .mu.m generation, the wiring pattern 11 is approximately 0.6 .mu.m in height and approximately 0.35 .mu.m in width, and requires being resistant to a current density of 1.times.10.sup.5 A/cm.sup.2.
Further, in LSI's of the 0.18 .mu.m generation, although the spaces between wiring patterns are reduced, thinning the wiring patterns to reduce capacitance between wiring patterns in a wiring layer constructed by wiring is needed in accordance with requirements of low power demands and high speed for LSI's.
To meet these demands, the cross-sectional areas of wiring patterns should further be reduced to improve electro-migration resistance, or a material having excellent electro-migration resistance should be selected and the electrical resistances of wiring patterns should be reduced.
In contrast to the method using an aluminum-based wiring material of the related art described above, there is a method using, as a wiring material, copper which has excellent resistivity and excellent electro-migration resistance.
In such a method, ordinary reactive ion etching can rarely be employed for forming a wiring pattern since a compound having a high vapor pressure can rarely be derived from copper. As a remedy for this, a buried wiring structure obtained by employing a CMP technique has been proposed. As to the buried wiring structure, a structure has been previously proposed in which a connecting plug from a lower layer is initially formed and only a wiring portion is then buried with copper or the like. In another proposal, the connection between wiring layers is also achieved with copper. Hereinafter, a so called Dual Damascene method is explained with reference to FIG. 2.
As shown in FIG. 2A, an insulating film 12 is provided on a semiconductor substrate 11, and further, a first wiring pattern 13 is formed on the insulating film 12.
Initially, on such a semiconductor substrate 11, a so-called Gap Fill insulating film and an insulating film to inhibit the generation of capacitance between wiring layers are deposited by a depositing technique such as a TEOS-type CVD method. After this, an interlayer insulating film 14 having a smooth surface is formed by a smoothing technique such as CMP. Next, an etching-termination insulating film 15 is provided on the above-mentioned interlayer insulating film 14 by a CVD method, and then an inter-wiring insulating film 16 is further provided.
Hereupon, the interlayer insulating film 14 is formed so as to have a thickness of, for example, approximately 0.6 .mu.m, with which the inter-wiring-layer capacitance in the first wiring pattern 13 does not matter.
Next, as shown in FIG. 2B, a resist film 17 is provided on the above-mentioned inter-wiring insulating film 16 by an ordinary coating technique, and openings 18 are formed by a lithography technique in the resist film 17 at portions where wiring is to be done. Grooves 19 of approximately 0.6 .mu.m in depth, which corresponds to the desired heights of wiring patterns to be formed, are then formed in the inter-wiring insulating film 16 by etching using this resist film 17 as an etching mask. The reaction in this etching is stopped by the etching-termination insulating film 15.
Subsequently, as shown in FIG. 2C, after the above-mentioned resist film is removed, a resist film 20 is provided again by coating, and an opening 21 is formed by a photolithography technique in a portion for connecting with the first wiring pattern 13. While using this resist film 20 as an etching mask, a connecting hole 22 is then formed by etching the etching-termination insulating film 15 and the interlayer insulating film 14 until the first wiring pattern 13 is exposed. After this, the resist film 20 is removed.
Next, as shown in FIG. 2D, copper 23 for a wiring pattern is deposited by a CVD method so as to have a thickness thicker than the thickness from the interlayer insulating film 14 to the inter-wiring insulating film 16, for example, 1.5 .mu.m.
After this, copper 23 in the portions other than the inside of the grooves 19 and the inside of the connecting hole 22 is removed by polishing using a CMP technique in conditions suitable for metal polishing. As a result, as shown in FIG. 2E, a connecting plug 24 is formed inside the connecting hole 22, and also, second wiring patterns 25 are formed inside the grooves 19.
In the method according to the related art described above, the grooves 19 for forming the second wiring patterns 25 are initially provided, and after this, the connecting hole 22 for forming the connecting plug 24 is provided by etching. This procedure may be performed in the reverse order.
In VLSI's of the 0.18 .mu.m generation or later, the widths of wiring patterns will be increasingly narrowed, namely, approximately 0.22 .mu.m by the 0.18 .mu.m generation, and approximately 0.15 .mu.m by the 0.13 .mu.m generation. Further, as to electrical resistance, it is anticipated that 0.29 .OMEGA./.mu.m or less will be required for the 0.18 .mu.m generation and 0.82 .OMEGA./.mu.m or less will be required for the 0.13 .mu.m generation.
When aluminum is solely used for wiring, however, since the mass of aluminum is low, scattering of aluminum atoms occurs due to collisions with numerous electrons at wiring portions subjected to flows of electrical currents in high current densities. This leads to a partial breakage of the wiring pattern during uses for long time periods, and finally, results in disconnection. Accordingly, since breakage by so-called electro-migration may be caused, electrical currents having high current densities cannot be made to flow through the wiring pattern.
Further, when an aluminum-based metal which principally comprises aluminum and contains copper having a mass larger than that of aluminum in a content of, for example, approximately 0.5% is used for wiring, fine processing is difficult since the residue of poorly reactive copper is readily generated during a process of reactive ion etching. Additionally, copper is rarely dispersed at aluminum grain boundaries homogeneously and highly concentratedly, and therefore, the addition of 0.5% or more of copper is substantially impossible.
Meanwhile, by the method in which tungsten plugs are formed, even fine connecting holes can be readily filled with a wiring material. Such a method, however, requires a process for depositing aluminum-based metal to be a wiring pattern after tungsten deposited on an interlayer insulating film is removed. Accordingly, the time period of the process for forming wiring layers becomes long, the turnaround time increases, and therefore, the produced LSI's become expensive. Further, when this method is employed as an interconnecting method for LSI's of the 0.18 .mu.m generation or later, connecting holes to be formed should have slant sidewalls in order to pack tungsten therein without formation of a blowhole since the connecting holes are approximately 0.20 .mu.m in diameter and approximately 3 in aspect ratio. This requires larger diameters of the connecting holes, and therefore, is unsuitable for manufacturing finer LSI's.
Furthermore, the above-described LSI specifications can rarely be achieved by using an aluminum-based wiring material or by employing a method including formation of tungsten plugs. Accordingly, the wiring material should be a material having low electrical resistance and excellent electro-migration resistance, such as copper or a copper-based alloy.
Moreover, as shown in the layout diagram FIG. 3, connecting holes 5 are formed in an interlayer insulating film (not illustrated) to connect first wiring patterns as lower wiring patterns (not illustrated) with second wiring patterns 7 formed thereabove. For providing the above-mentioned second wiring patterns 7 so as to fill the connecting holes 5, the widths of the second wiring patterns 7 should be determined considering margins for arrangement deviation (hereinafter, simply referred to as "margin") relative to the connecting holes 5. In other words, the width wl of a second wiring pattern located above a connecting hole 5 should include a margin d (in FIG. 3, a margin of d/2 is provided on each side of a second wiring pattern located above a connecting hole). Such a design requires a wider inter-wiring spaces D increased by the margin of d/2, and therefore, is disadvantageous for manufacturing finer LSI's.
In the above-described Dual Damascene method, a connecting hole is formed upon a wiring groove which has been previously formed, or a connecting hole or a wiring groove is formed upon a connecting hole which has been previously formed. Due to this, in the lithography process to be performed, a resist pattern should be formed on a uneven surface. The formed resist pattern, therefore, tends to be deformed due to, for example, light reflection at uneven portions. This can be a disadvantage in manufacturing finer LSI's.
Further, this method requires two etching processes. Specifically, a groove is formed through a first etching process, a lithography process is then carried out, and a connecting hole is formed through a second etching process. In addition, the second etching process is complicated since the process is generally performed by continuously etching an etching-termination insulating film constituted with silicon nitride and an interlayer insulating film constituted with silicon oxide. Specifically, the etching conditions such as an etching gas and plasma electrical power should be altered so as to be suitable to each insulating film. Accordingly, substantially three etching processes should be carried out.
Moreover, in the Dual Damascene method according to the related art, as shown in FIG. 4A, when arrangement deviation e between a groove 19 and a resist opening 21 is generated in a process for forming the resist opening 21 in a resist film 20, a connecting hole 22 which is formed so as to transcript the resist opening 21 by subsequent etching with a mask of the resist film 20 is deviated relative to the groove 19.
In other words, as shown in FIGS. 4B and 4C, the connecting hole 22 is formed at a position deviated by e relative to the groove 19. Due to this, the space s between a connecting plug 24 formed in the connecting hole 22 and a second wiring pattern 25 (25b) on the side to which the connecting hole 22 is deviated becomes narrower than the previously designed value by the value of the arrangement deviation. To form second wiring patterns 25 (25a and 25b) with a sufficient space s, the second wiring patterns (corresponding to the grooves 19) should be formed with a space between the second wiring patterns 25 (the grooves 19), the space being enlarged by the value e of arrangement deviation. This enlargement is disadvantageous in manufacturing finer LSI's.